The present invention relates generally to integrated circuits including internal memory and, more particularly, to methods and circuitry for testing integrated circuits.
In order to ensure operation of a memory of an integrated circuit, such as an SRAM memory, it is known to perform a test of the memory. The test may be a built-in self-test.
It is also known to test operation of some or potentially all components of the integrated circuit by performing a scan test. In the scan test flip-flops of the integrated circuit are used to form one or more serial scan chains into which data is loaded to initialize components of the integrated circuit into a known state. Then, after a period of operation of the integrated circuit, the scan chain is used to store the state of the components with data indicative of the state being unloaded from the scan chain for comparison with an expected state.
However, as integrated circuits get ever larger, testing becomes increasingly more complex and time consuming. Furthermore, it is increasingly desired to exercise more control over the testing of such integrated circuits.